XC2S Series: The Spartan®-II FPGA family

The Spartan®-II Field-Programmable Gate Array family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The six-member family offers densities ranging from 15,000 to 200,000 system gates. System performance is supported up to 200 MHz. Features include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs. Fast, predictable interconnect means that successive design iterations continue to meet timing requirements.The Spartan-II family is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs).

Features

• Second generation ASIC replacement technology
    - Densities as high as 5,292 logic cells with up to 200,000 system gates
    - Streamlined features based on Virtex® FPGA  architecture
    - Unlimited reprogrammability
    - Very low cost
    - Cost-effective 0.18 micron process
• System level features
    - SelectRAM™ hierarchical memory:
        · 16 bits/LUT distributed RAM
        · Configurable 4K bit block RAM
        · Fast interfaces to external RAM
    - Fully PCI compliant
    - Low-power segmented routing architecture
    - Full readback ability for verification/observability
    - Dedicated carry logic for high-speed arithmetic
    - Efficient multiplier support
    - Cascade chain for wide-input functions
    - Abundant registers/latches with enable, set, reset
    - Four dedicated DLLs for advanced clock control
    - Four primary low-skew global clock distribution nets
    - IEEE 1149.1 compatible boundary scan logic
• Versatile I/O and packaging
    - Pb-free package options
    - Low-cost packages available in all densities
    - Family footprint compatibility in common packages
    - 16 high-performance interface standards
    - Hot swap Compact PCI friendly
    - Zero hold time simplifies system timing
• Core logic powered at 2.5V and I/Os powered at 1.5V, 2.5V, or 3.3V
• Fully supported by powerful Xilinx® ISE® development
system
    - Fully automatic mapping, placement, and routing
 
For further information please view it online: XC2S150 (pdf | 99 pages)

This Spartan-II FPGA data sheet is in four modules :
Module 1: Introduction and Ordering Information
    • Introduction
    • Features
    • General Overview
    • Product Availability
    • User I/O Chart
    • Ordering Information
 Module 2: Functional Description
    • Architectural Description
        - Spartan-II Array
        - Input/Output Block
        - Configurable Logic Block
        - Block RAM
        - Clock Distribution: Delay-Locked Loop
        - Boundary Scan
    • Development System
    • Configuration
        - Configuration Timing
    • Design Considerations
Module 3: DC and Switching Characteristics
    • DC Specifications
        - Absolute Maximum Ratings
        - Recommended Operating Conditions
        - DC Characteristics
        - Power-On Requirements
        - DC Input and Output Levels
    • Switching Characteristics
        - Pin-to-Pin Parameters
        - IOB Switching Characteristics
        - Clock Distribution Characteristics
        - DLL Timing Parameters
        - CLB Switching Characteristics
        - Block RAM Switching Characteristics
        - TBUF Switching Characteristics
        - JTAG Switching Characteristics
Module 4: Pinout Tables
    • Pin Definitions
    • Pinout Tables